1. Field of the Invention
The present invention relates to a control system for multiple channel data transfers between buses in a processing system. More particularly, the present invention control system employs a controlled timed multiplexed data transfer system which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access conflicts.
2. Description of the Prior Art
Control systems for transferring data to and from main storage units (MSU's) and input/output (I/O) peripheral devices are well known. Such systems are classified in International Class GO6F 13/32 and in U.S. Class 364, Subclass 200. Requests for transfer of data can be routinely handled by settling priorities for each of the units or devices which may raise requests for transfer of data to another unit or device of the processing system.
One commonly known processing system is provided with a system bus (or main processor bus) to which the CPU (or CPU's) and main storage units (MSU or MSU's) are connected. In addition, the input/output peripheral devices (I/O's) are connected to a data bus (D-Bus). The control system for the transfer of data between the main bus (M-Bus) and the data bus may reside in an input/output processing system (IOP) connected between the two buses. As the computing system becomes larger and presumably faster no part of the control system is performed by the CPU or CPU's, but is performed by input/output processors (IOP's).
The function of the IOP's is to transfer data between the main bus and the data bus as efficiently as possible. When priorities are set for the channels attached to the data bus there is always a conflict between requests for access to the main system bus and the data bus which must be resolved by the control system.
It is a desirable feature of the present invention to provide an improved I/O control system which eliminates conflicts between requests from channels and I/O devices and does not delay or interfere with control data transfer signals.